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Thank you again Hlide, this will help a lot!

It was a long time ago since you tried to use the ARM backend? Btw, llvm-gcc 4.0 is abandoned now, only 4.2 is maintained. Yes, it is being developed in llvm trunk. To checkout : http://tinyurl.com/6nf9la The backend src is at : trunk/lib/Target/Mips LLVM targets are developed as libraries inside ll...

Hi hlide, I'm working on implementing support for the Allegrex Core into LLVM Mips backend. LLVM, among other things, is a compiler infrastructure (www.llvm.org) which provides aggressively optimizations. I have a lot of cool long term plans, like supporting intrinsics for the VFPU, etc... But now I...

On the Mips R4000 User Manual we have: Is 32-bit binary fixed-point instructions supported on Allegrex FPU? "In the instruction formats shown in Tables 6-9 through 6-12, the fmt appended to the instruction opcode specifies the data format: S specifies single-precision binary floating-point, D s...

nice explanation! The "pitch" name makes pipeline discussions easier. ;) The allegrex FPU support double precision instructions using aliased registers? By aliased i mean a double precision instruction that uses 2 32-bit registers for each operand and for the result (i know this is support...

ok. but what about the wiki, the info about FPU latency there is wrong, right?
"for standard FPU : cycles are probably the same as R4400's with a usual pitch of 1 cycle and a latency of several cycles."
what do you mean by pitch?

that is very strange, since this info is labeled under FPU, and there is also another topic about VPFU... i really just need some real info

Hi, I'm curious about FPU instruction latency! It happens that on ps2dev wiki i found : "Sqrt (28 cycles), div(28 cycles), most others 1 cycle" while in R4000 user manual - http://tinyurl.com/5qjlxt page 174 - we have different values. So, if the R4000 FPU used in PSP has different latency...

I found!
http://forums.ps2dev.org/viewtopic.php?t=6929
Thanks

Where can I find the complete list of VFPU instructions?