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The PS2 VU documentation says VU0 will halt and interrupt on a watchdog if it runs too long. This is probably so that an out-of-control VU0 doesn't create a situation that prevent access to the VU1 control registers. Unfortunately, it doesn't appear to be documented what thresholds trip that watchdog. Anyone know ?

Gorim

Huh wich page in the vu manual did you get that from ?
and well frankly I dont see the point you can always stop/start vu0 from ee core.

blackdroid wrote:Huh wich page in the vu manual did you get that from ?
and well frankly I dont see the point you can always stop/start vu0 from ee core.

• 1. VU User's Manual, p201, COP2 registers are used for VU0 control registers.
  2. VU User's Manual, p204, co-processor transfer instructions are used to access the VU0 control registers.
  3. VU User's Manual, pp216,232,etc..., variants of QMTC2, CFC2, etc...can interlock on a running VU0, until the VCALLMS'ed microroutine completes.
  4. EE User's Manual, p28, INT_VU0WD (interrurpt 14, VU0 in RUN status for a long time continuously, forcebreak sent to VU)

Summary: As you point out, one can send their own forcebreak to VU0, but it requires a COP2 transfer. However, depending on the situation, a COP2 transfer instruction can be chosen to interlock with a running VU0 or to not interlock. In the former situation, a risk is created that a VCALLMS microroutine will not stop. As long as interlocked transfer instructions are used, access to VU0 and VU1 control registers are blocked. The easy way around this is to not interlock, but the option to *use* interlock is available for a reason, thus the watchdog on VU0 would also be necessary for a worst case scenario where one needs to regain control of VU0.

Yes, the manual doesn't come right out and directly state what I originally posted, but sometimes you just gotta read between the lines, no ? :)

Gorim

first time I actually caught the watchdog word on the interrupt table presentation.
guess you need to time it :)