forums.ps2dev.org

The VU1 registers are mapped into the VU0s micromem address space,
thus allowing VU0 to move data to the general registers and manipulate
the control registers.

But one item missing from all diagrams I have seen is how wide is the
bus linking the two together ? Or are the registers actually physically
located on VU0 and accessed directly by VU1 ?

Just curious...

Gorim

The VU's are two seperate units, that both live on the EE chip. I don't believe that VU1 registers live somewhere on VU1, but who knows how all of that is jury-rigged. Most of the I/O mappings to VU space from the EE are TLB-mapped anyway (yeah I know that doesn't apply to VU0 micromem). I don't know if there is a bus linking them, but what difference does it make how wide it is if there is one? :P.

mrbrown wrote:[..]. I don't know if there is a bus linking them, but what difference does it make how wide it is if there is one? :P.

Well, in order for a VU0 program to write directly to Vu1 registers, it must communicate over a bus linking the two, unless somehow it uses the main EE bus to do so. But I do not think that is the case, since many various Sony bus diagrams of the EE show a path from VU0 to VU1. This is also the only path where a bus width isn't indicated in either the diagrams or literature.

What difference does it make ? Not a heck of alot. It was purely an academic question so that this forum doesn't go fallow, as opposed to feral :) I suppose it would matter if someone wanted to write code where VU0 and VU1 must operate serially in a high performance situation. As a networking kind of guy, I naturally think alot about bandwidths from point A to point B so these kind of academic questions interest me.

Now I am running out of questions to ask in this forum, but I have about 2 months to think of another, thats about the average time between questions here I think ;)

Gorim

Gorim, it could be nice to propose all those things you learn into a kind of VU faq... There is so much information ion this forum...