The r4000/r4400 manual states that "CTCz x, y" (move general register x to _control_ register y of Coprocessor(z)) and "CFCz x, y" are not valid z=0 (as in, coprocessor 0 has no _control_ registers.)
Apparantly this is not the case for Allegrex. Someone mentioned that they spotted CTC0 and CFC0 in a partial disassembly. I wrote some code to output all 32 "control" registers of CP0, and I can't really make sense of it, but someone with a firmware dump should find every case of CTC0 and CFC0 instructions and record the operands, so we can figure out just which of these registers are actually being used.
cp0c $0: [08900d78]cp0c $1: [00212180]cp0c $2: [20000403]cp0c $3: [00008400]
cp0c $4: [00000000]cp0c $5: [00001006]cp0c $6: [00212180]cp0c $7: [00212180]
cp0c $8: [8801ea00]cp0c $9: [8801cdc8]cp0c$10: [8801ce30]cp0 $11: [88021e74]
cp0c$12: [a802368c]cp0c$13: [000000fc]cp0c$14: [881b80c0]cp0c$15: [00000000]
cp0c$16: [88227668]cp0c$17: [20040420]cp0c$18: [8801ec38]cp0c$19: [2004b22a]
cp0c$20: [00212180]cp0c$21: [3c821600]cp0c$22: [fffffc34]cp0c$23: [de6bb002]
cp0c$24: [ba0b48f4]cp0c$25: [00000000]cp0c$26: [00212180]cp0c$27: [ccc6b9f4]
cp0c$28: [8801ec10]cp0c$29: [00212180]cp0c$30: [6ac408c0]cp0c$31: [00212180]
ctc0/cfc0 instructions
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chrismulhearn
- Posts: 80
- Joined: Wed Feb 22, 2006 4:43 am
This is a fantastic tool.
As your google is broken ;-) ... heres a link:
http://www.hitmen-console.org/ --> Playstation portable --> Releases -->pspinside v0.9q
As your google is broken ;-) ... heres a link:
http://www.hitmen-console.org/ --> Playstation portable --> Releases -->pspinside v0.9q
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chrismulhearn
- Posts: 80
- Joined: Wed Feb 22, 2006 4:43 am
Ahhh I assumed he was talking about a PLACE. oops! Should have googled. Plus my eyes have whizzed right by the word "psplink" about 1000 times in the last month.
I will have to check that tool out.
But anyone who already has a disassembly should be able to find out what arguments are being sent to ctc0 and cfc0, and then they should tell me. :-)
Perhaps we should start an "Allegrex CPU" thread, dedicated entirely to the mysteries inside this ASIC?
I will have to check that tool out.
But anyone who already has a disassembly should be able to find out what arguments are being sent to ctc0 and cfc0, and then they should tell me. :-)
Perhaps we should start an "Allegrex CPU" thread, dedicated entirely to the mysteries inside this ASIC?
The control registers are used by the kernel for general purpose stuff, for example when an exception occurs it stores v0/v1 in I think control registers 4 and 5 at the start of the exception then uses them v0/v1 as general purpose regs, later exception handlers can then restore the values of v0/v1 at a later date.
They also use it again in exceptions to point to the dispatch tables for the various exception types, and one of them also points to the control block which is used to determine syscall dispatch.
Basically they are just simple non-gpr registers used by the kernel for what ever it feels like, there is no special significance to them and they could change from firmware revision to firmware revision.
They also use it again in exceptions to point to the dispatch tables for the various exception types, and one of them also points to the control block which is used to determine syscall dispatch.
Basically they are just simple non-gpr registers used by the kernel for what ever it feels like, there is no special significance to them and they could change from firmware revision to firmware revision.