load delay

[johnmph]

Hello, i would like to know why this small code works :

Code: Select all

.set noreorder

	.global	func
	.ent	func

func:

	lw $a2, 0x0($a0)
	sw $a2, 0x0($a1)

	jr $ra
	nop

	.end func

In the mips documentation, load in memory uses delay : "you *must* have an instruction following a load that does not use the result of the load".

However, this code uses the result of the load immediately after and he works.

Is what it is because the compiler arranges the code ? (even with .set noreorder directive ?)

[ector]

No modern MIPS CPU:s that I know of have this limitation. They all added forwarding, fixing this problem, in something like 1992. What documentation are you reading?

[BlackDiamond]

Modern MIPS CPUs can (partially) stall the pipeline and wait for the result to be availiable. So no interlaced instruction is needed but the delay is still here.

[groepaz]

conclusion, make it

Code: Select all

  
   lw $a2, 0x0($a0) 
   jr $ra 
   sw $a2, 0x0($a1) 

:)

[BlackDiamond]

yep, got rid of the 2 wasted cycles :)

[johnmph]

Thanks all.

conclusion, make it

Code: Select all

  
   lw $a2, 0x0($a0) 
   jr $ra 
   sw $a2, 0x0($a1) 

:)

yes, it's the code that i will use.

[johnmph]

one more question :

write in memory has also a delay like read ?
In documentation, it talks about load only.

Thanks

[johnmph]

one more question :

write in memory has also a delay like read ?
In documentation, it talks about load only.

Thanks

oups, stupid question.

Even if write has a delay, registers are not affected and even if i read memory just after having written this memory, load creates a delay, thus no problem ;-)