I feel I'm a noob in MIPS again. I'm doing some reading on its instruction set. I'm wondering if we use these instructions, how will the chip act, error 'FEATURE_NOT_AVAILABLE' ?
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
TLBP Probe TLB for Matching Entry
TLB question
Re: TLB question
First, Allegrex uses a FM MMU (that is a Fixed Mapping Memory Manager Unit) instead of a TLB MMU. Worse, Allegrex doesn't seem to provide a TLB MMU since COP0 registers don't even answer anything when interrogating the TLB-relative registers. I don't try the TLB-relative instructions but i'm quite sure they would raise a Reserved Instruction exception as it would be with trap instructions which are not implemented into Allegrex.gbj1 wrote:I feel I'm a noob in MIPS again. I'm doing some reading on its instruction set. I'm wondering if we use these instructions, how will the chip act, error 'FEATURE_NOT_AVAILABLE' ?
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
TLBP Probe TLB for Matching Entry
So just forget them.
if you are refering to the ability for protecting the read/write access right to kernel/user code, that is not because of MIPS cpu had this but rather because of a BCU (Bus Control Unit), the registers of which are mapped in memory allegrex (0xBC2000xx if i'm not wrong). You may call it a MPU but it is not its solely function.gbj1 wrote:I have heard a sort of memory management unit called 'MPU' (memory protection unit). Allegrex seems to have such a unit to protect its kernel memory.
Sony devs had their unlimited wisdom guided to choose such a chip on their portable game console.
I'm not against the fact that Sony drops the TLB management since it would rather slow games down (standard MIPS uses a software TLB management, not a hardware one like ix86).
And Sony never uses the TLB available on PSX for their games too for the same reason.