Hi Guys,
Daedalus so far is quite impressive however i'm sure many of you would like to see it achieve what its supposed to and to prove that N64 emulation clearly is possible on the PSP.
So far raphael and hlide gave StrmnNrmn small tips that improved daedalus a whipping 10 - 15% in performance. Surely this makes it clear that not everyone needs knowledge of the N64 processor to make things work.
You probably are thinking, Why doesn't Wally do it himself. I don't have the knowledge to help optimize ANYTHING in any programming language. I would if I did, that's for sure. The only thing i can do is correct GFX issues. Which is the whole point of Daedalus Spiff Up.
Would be great if anyone had advice :)
Wally..
Help improve Daedalus for us all
1) for 32-bit float operations on N64 you may generate vfpu instructions and reserve 32 vfpu registers (2 matrixes) for a direct mapping with those 32 fpu registers of N64. This is only good if 32-bit fpu is heavily used.
2) use FILL WITH LOCK cache operations to reserve some memory where you map your N64 registers. Those cache lines being locked you should be able to avoid slow access in main memory when you need to update temporary registers from/to N64 registers mapped in memory. However if you need to invalidate the d-cache, don't forget to "writeback" them before any invalidation and to re-"fill with lock" them after any invalidation and before any access to registers mapped into memory.
a cache line being 64 bytes, that is, 16 x 32-bit registers or 8 x 64-bit registers.
2) use FILL WITH LOCK cache operations to reserve some memory where you map your N64 registers. Those cache lines being locked you should be able to avoid slow access in main memory when you need to update temporary registers from/to N64 registers mapped in memory. However if you need to invalidate the d-cache, don't forget to "writeback" them before any invalidation and to re-"fill with lock" them after any invalidation and before any access to registers mapped into memory.
a cache line being 64 bytes, that is, 16 x 32-bit registers or 8 x 64-bit registers.