After reading up about the PSP, I was wondering if the data cache and the instruction cache really the Scratchpad? Is it accessable in user mode?
Also, what is the difference between cached and uncached memory (ex. 0x08800000 vs 0x48800000)? I would guess that the cached area checks to see if it has the data in cache to save time while the uncached immediately loads its, but I'm not sure if this logic is completely true (or completely false). *Edit* I understand that my guess was correct for this. Still need help with the first question.*
I would really appreciate some info.
Questions about the Scratchpad and cached/uncached memory
The scratchpad (4 KiB) is not the same as CPU's L1 cache (32 KiB). The scratchpad is at 0×00010000 but I think it is also remapped along with the pre-IPL so in any case its impossible to access the scratchpad from user/kernel mode after the IPL has executed as its memory address address is remapped to another location.
When using a pointer, if you OR it with 0x40000000, it becomes a pointer to uncached memory. It still points to the same address. Since the PSP only has 32/64 MB, the unused address bits on the left are used for this purpose (well its actually for most MIPS CPUs). This means that if you write to the pointed address it performs a write-through and the value is updated in the RAM immediately. I'm not sure if it applies to reading as well. This is used when writing variables to be used by GU functions, since the GU cannot see the data cache of the CPU.
When using a pointer, if you OR it with 0x40000000, it becomes a pointer to uncached memory. It still points to the same address. Since the PSP only has 32/64 MB, the unused address bits on the left are used for this purpose (well its actually for most MIPS CPUs). This means that if you write to the pointed address it performs a write-through and the value is updated in the RAM immediately. I'm not sure if it applies to reading as well. This is used when writing variables to be used by GU functions, since the GU cannot see the data cache of the CPU.