The PS2 VU documentation says VU0 will halt and interrupt on a watchdog if it runs too long. This is probably so that an out-of-control VU0 doesn't create a situation that prevent access to the VU1 control registers. Unfortunately, it doesn't appear to be documented what thresholds trip that watchdog. Anyone know ?
Gorim
Whats the threshold on the VU0 watchdog ?
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blackdroid wrote:Huh wich page in the vu manual did you get that from ?
and well frankly I dont see the point you can always stop/start vu0 from ee core.
- 1. VU User's Manual, p201, COP2 registers are used for VU0 control registers.
2. VU User's Manual, p204, co-processor transfer instructions are used to access the VU0 control registers.
3. VU User's Manual, pp216,232,etc..., variants of QMTC2, CFC2, etc...can interlock on a running VU0, until the VCALLMS'ed microroutine completes.
4. EE User's Manual, p28, INT_VU0WD (interrurpt 14, VU0 in RUN status for a long time continuously, forcebreak sent to VU)
Yes, the manual doesn't come right out and directly state what I originally posted, but sometimes you just gotta read between the lines, no ? :)
Gorim
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